Apple’s, nearly 1000 member strong, in-house processor design team is really working hard on speeding up Macs and iOS devices.Instruction pipeline example

Patently Apple reports that Apple filed a trademark application for the term “Macroscalar” in the US and Hong Kong. The term concerns microprocessors found on computers, more specifically, it refers to a type of architecture for processors that Apple is developing.

Apple, as MacRumors points out, typically gets their trademarks first registered in countries like Trinidad and Tobago, and only after it releases a product does it apply for trademarks in countries like the US. And indeed, a trademark application for the term “Macroscalar” was filed in Trinidad and Tobago August last year.

Apple Macroscalar trademark

The Macroscalar architecture is in development at Apple since 2004, with (at least) four patents being granted to the company till now.

The architecture aims to speed up performance by altering the way code is compiled.

Almost every modern processor architecture implements a technique called “instruction pipeline,” which increases the number of instructions executed per cycle by executing different stages of multiple instructions in parallel. The longer the pipeline, the better the throughput. This image from Wikipedia perfectly explains the technique, where one stage of each instruction is being completed in one cycle.

Instruction pipeline example

Typically loops cause a break in this pipeline, since the number of times a loop would run cannot be known before run time, which means the next instruction to be executed can’t be predicted beforehand.

ZDNet explains how Apple’s macroscalar architecture handles this problem:

The macroscalar processor addresses this problem in a new way: at compile-time it generates contingent secondary instructions so when a data-dependent loop completes the next set of instructions are ready to execute. In effect, it loads another pipeline for, say, completing a loop, so the pipeline remains full whether the loop continues or completes. It can also load a set of sequential instructions that run within or between loops, speeding execution as well.

This means that the macroscalar architecture would have two pipelines, one would hold the instructions to be executed while the loop is running, and the other for instructions to be executed after the loop terminates. Depending on the conditions, one of the two pipelines could be chosen, avoiding the “break” in pipeline and ensuring a good throughput.

Apple’s advantage isn’t just that. In fact, a lot of companies have come up with enhanced processor architectures which, in theory, could boost performance multi-fold. Apple’s advantage is its tight control over its product line, especially iOS devices.

A lower degree of fragmentation coupled with the fast adoption of newly released iOS devices, would mean that the potential boost due to this new architecture would benefit a large percentage of users within a short amount of time. This gives developers a huge incentive to optimize their code for this new architecture.

We’ve already seen a similar phenomenon when Apple launched the Retina display equipped iPhone 4. Most developers, within a very short period of time, started updating their apps with Retina display optimized images.

We’d conclude the same way ZDNet did in their report on Macroscalar architecture:

Is it a breakthrough? It could be if the efficiencies it promises can be realized in practice. We’ll have to see just how good Apple’s compiler engineers are.

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